1. Field of the Invention
The present invention relates to a multi-chip package (hereinafter, referred to as the “MCP”) encapsulating a plurality of semiconductor chips in one package, and specifically to a technology for reducing the wiring capacitance of a wiring chip used for wire-bonding the plurality of semiconductor chips.
2. Description of the Related Art
Recently, MCPs encapsulating a plurality of semiconductor chips for different purposes in one package are widely used. For example, a plurality of memory chips for different purposes are stacked on one MCP substrate, and an ASIC (Application Specific Integrated Circuit), for example, a memory controller or other devices are stacked thereon. For stacking elements in an MCP, it is common to use wire bonding for connecting a memory chip and an ASIC.
However, wire bonding involves limitations such as the wire length or the like. In addition, where a memory chip has a large size, it is difficult to connect an ASIC stacked on the memory chip directly to the MCP substrate by wiring. Therefore, a wiring chip is generally used as described in Japanese Laid-Open Patent Publication No. 2004-327993.
The wire used for wire bonding can be bent into a loop in a height direction (the direction vertical to a joint plane at which the semiconductor chip is jointed with the circuit substrate), but cannot be bent into a loop in a transverse direction (the direction parallel to the joint plane). Therefore, a relay chip for direction conversion is used as described in Japanese Laid-Open Patent Publication No. 2004-056023.